This invention relates to a simplified DSCP (Double Short-Circuited-Poly) process for making non-self-aligned semiconductor memory cells of the FLOTOX EEPROM type.
There exists a well-recognized demand, from the semiconductor integrated circuit market, for large capacity ( greater than 256 kbit) EEPROM devices. This implies increased effort on the part of the manufacturers of such circuits to provide circuit devices of an ever smaller size.
A memory cell of the EEPROM type comprises a field-effect transistor having a floating gate which is coupled capacitively to a control gate terminal. This floating gate transistor is connected in series with a selection transistor.
The floating gate comprises a first layer of polysilicon, referred to as the poly1, and the control gate comprises an overlying second layer of polysilicon, or poly2. Whereas in the memory cell the poly1 and poly2 layers are isolated by an intermediate dielectric (interpoly) layer, in the selection transistor these layers are in contact with each other.
A DSCP process flow requires that the first polysilicon layer of the selection transistor associated with the memory cell be contacted, for otherwise, the selection transistor would be floating all the time. A special mask (matrix mask) is used for this purpose which allows the poly1 and poly2 layers to be short-circuited by removal of the intermediate dielectric layer from appropriate areas, for example, every n bytes.
In this way, the poly1 layer of the selection transistor is coupled to a signal transmitted by the poly2 layer through the direct contact with the poly2 layer.
In a standard DSCP process, the control gate and select regions are defined by means of a special etching step, known as the self-aligned etch, whereby the stacked poly1/interpoly/poly2 layers are etched sequentially and are vertically aligned. For this reason, the distance of the selection transistor from the memory cell proper should be adequate to prevent short-circuiting of the respective gates, as may be due to polysilicon left over from the self-aligned etch.
In theory, a non-self-aligned cell could be used to define the selection and control gate regions by specific etching steps, to eliminate the problem caused by poly residue. But in a DSCP process, such a solution would entail a serious loss in circuit area.
In addition, a self-aligned process leaves ditches in the source line, which can result in serious malfunctioning of the memory device.
Embodiments of this invention provide a simplified DSCP process which has such features as to allow non-self-aligned semiconductor memory cells of the FLOTOX EEPROM type to be made, while keeping the cell bulk low.
One of the concepts behind embodiments of this invention is to incorporate steps of a non-self-aligned process to a DSCP process, thereby obviating the aforementioned drawbacks of self-aligned processes and the need for increased overall bulk of the cell.
The features and advantages of a process according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.